1. Field of the Invention
The present invention relates to a photomask having an alignment mark for the current layer, particularly relates to a mask of  shape extra-scribe lane which is applicable to be used to improve the mask area used efficiency.
2. Description of Related Art
Under the condition of the higher integration and the smaller size of the process in the semiconductor process they are, the harder and more complicated steps of the process they are. Therefore, it becomes the direction what the manufacturers are trying hard to reach as how to proceed process monitor while using the real-time measuring apparatus in order to react the real-time problem and lower the loss causing by the mistakes made in process.
In general, aside from a proper control of the critical dimension, the yield of a wafer after a photolithographic process also depends on alignment accuracy. Thus, the alignment accuracy of the measurement is an important part in the semiconductor process.
FIG. 1 is a planar view of a photomask with alignment mark for the current layer.
Referring to FIG. 1, wherein a main pattern 102 of a photomask 100 usually includes a device pattern, a line pattern, etc. However, an inter-scribe lane pattern 104 is between the main pattern 102 as well as an extra-scribe lane pattern 106 which is sited on the four edges of the photomask 100. The exposure shot maps are designed and set recipe into the exposure tool such as scanner exposure system or stepper exposure system, the four extra-scribe lanes are over lay to the four nearby shot map specifically. Further, sets of the alignment marks for the current layer 108a and 108b are sited on the extra-scribe lane pattern 106 of the photomask 100 in order to make sure whether the shot maps are well setting at the exposure tool and at the correct location at the wafer. Due to the extra-scribes are over lap, the alignment marks for the current layer 108a and 108a will add to form a pattern shown in FIG. 2 by double exposure.
FIG. 2 is a perspective view of photo resist by using conventional photomask in FIG. 1 to process the exposure and development.
Referring to FIG. 2, after processing the stepping exposure and development of the alignment marks for the current layer 108a and 108b, in which one is a outer square-block and the other one is a inner square-hole in FIG. 1, a frame 200 will be formed just like the outer frame 202 and alignment mark for the current layer 108a formed on the chip scribe-lane as well as the inner frame 204 and alignment mark for the current layer 108b. Therefore, it is applicable to use the microscope apparatus to observe the frame after the stepping exposure and development to determine whether the exposure shot map accuracy is qualified in different steps.
However, under the condition of the higher the integration is in the semiconductor process, the more main pattern shall be expected to be existed in the limited area by the photomask design.